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GATE 2019 - Computer Organization Quiz-3 ( DataPath and Control Unit ) (App update required to attempt this test)
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Question 1
Consider the following reservation table for a pipeline having three stages S1, S2 and S3.
The minimum average latency (MAL) is_________.
The minimum average latency (MAL) is_________.
Question 2
Determine the width of Micro-instruction having following Control signal field, in a vertical Micro-programmed Control Unit
a) Next Address field of 5 Bits
b) ALU Function field selecting 1 out of 7 ALU Function
c) Register-in field selecting 1 out of 15 Registers
d) Register-out field selecting 1 out of 15 Registers.
e) Shifter field selecting no shift, right shift or left shift
f) Auxiliary control field of 3 bits
a) Next Address field of 5 Bits
b) ALU Function field selecting 1 out of 7 ALU Function
c) Register-in field selecting 1 out of 15 Registers
d) Register-out field selecting 1 out of 15 Registers.
e) Shifter field selecting no shift, right shift or left shift
f) Auxiliary control field of 3 bits
Question 3
Pipelining is a unique feature of
Question 4
Which of the following is an application of RISC architecture by adding more instructions
Question 5
For Instruction, SUB R1,(R2)+ operand fetch will not have_______ control signal.
Question 6
Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction
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Jun 25GATE & PSU CS