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GATE 2019 - Computer Organization Quiz-5 ( instruction Pipeline ) (App update required to attempt this test)
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Question 1
The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _________ percent.
Question 2
Which of the following statements is false regarding to instruction pipelining?
Question 3
A CPU has five stage pipeline and runs at 2.4 
frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch evaluates the target address in the fifth stage of pipeline. The processor stops fetching new instruction following a conditional branch until the branch outcome is known.
Find the cycles per instruction (CPI) for this processor if
of the instruction are conditional.
frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch evaluates the target address in the fifth stage of pipeline. The processor stops fetching new instruction following a conditional branch until the branch outcome is known. Find the cycles per instruction (CPI) for this processor if
of the instruction are conditional. Question 4
The time delay for four segment pipeline is t1 = 50ns, t2 = 45 ns, t3 = 95ns, t4 = 30ns. The interface register delay time is tr = 5ns. The time to add 100 pairs of numbers in the pipeline is :(in microseconds)
Question 5
Consider an instruction pipeline which has speedup factor of 5 while operating with 70% efficiency. What could be the number of stages in the pipeline?
Question 6
A 5 stage pipelined processor has IF, ID, EXE, MEM and WB. WB stage operation is divided into two parts. In the first part register write operation and in the second part register read operation is performed. The latencies of all those stages are 300, 400, 500, 500 and 300 (in nano second) respectively. Consider the following code is executed on this processor
Find minimum number of nop instructions (no operation) to eliminate hazards without using operans forwarding. (Assume each instruction takes one cycle to complete its operation in every stage)
Find minimum number of nop instructions (no operation) to eliminate hazards without using operans forwarding. (Assume each instruction takes one cycle to complete its operation in every stage)
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Jul 9GATE & PSU CS
