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GATE 2019 - Computer Organization Quiz-8 ( I/O interface ) (App update required to attempt this test)

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Question 1

Consider a system employing an interrupt driven I/O for a articular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 micro seconds (i.e. jump to the interrupt service routine (ISR); execute it and return to the main program). Determine what fraction of processor time is consumed by this I/O device when it is interrupted for every byte.

Question 2

Which among the following is incorrect about DMA?

Question 3

Consider two processors P₁ and P₂ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P₂ takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P₁. If the clock frequency of P₁ is 1GHz, then the clock frequency of P₂ (in GHz) is _________.

Question 4

Which of the following is/are NOT true?
S₁: If the entire data has been transferred, the DMA controller terminates the connection without informing the processor.
S₂: During DMA transfer both the “CPU” and “the program that requested DMA”, can continue their execution.

Question 5

Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. Once the data is filled into interface buffer, the DMA controller takes over the bus and transfer it to main memory in 28 sec.
What percentage of time is the CPU in busy mode (approximately)?

Question 6

Consider a pipeline ‘x’ consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeline ‘y’ contain the same number of stages but EX stage is divided into 4 sub stages, (EX1, EX2, EX3 and EX4) with equal delay i.e. (8 ns/4) and ID stage is divided into 2 substages (ID1 and ID2) with equal delays of (5 ns/2). In the pipeline x and y memory reference instructions are not overlapped so the penalty of memory reference instructions in the pipeline ‘x’ is 4 cycles and in the pipeline ‘y’ is 8 cycles.
If the program contain 30% of the instructions are memory based instructions, what is the ratio of speedup of x to speedup of y?

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GATE & PSU CS Computer Organization and Architecture

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