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GATE 2019: Microprocessors Quiz 1
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Question 1
Which of the following statements is/are true.
(i) ECL RAMS are used as cache memory.
(ii) Time consumption of MOSFET memory is larger as compared to BJT memory.
(iii) In ROM random reading is possible.
(i) ECL RAMS are used as cache memory.
(ii) Time consumption of MOSFET memory is larger as compared to BJT memory.
(iii) In ROM random reading is possible.
Question 2
If the number of bits in input and output codes is 6 and 8 respectively for a ROM.
The memory of this chip equal to
The memory of this chip equal to
Question 3
A digital computer has a memory unit with 20 bits per word. The instruction set consists of 120 different operations. Each instruction is stored in 1 word of memory and consists of operation part and address part. The number of words can be accommodated by the memory unit are
Question 4
What memory address range is NOT represented by chip #1 and chip #2 in figure? A0 to A15 in this figure are the address lines and CS means Chip Select. Which one of the following is not performed by this sequence?
Question 5
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is __________ .
Question 6
In the circuit shown in figure, A is a parallel in, parallel–out 4–bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4–bit bus, W. Its output acts as the input to a 16 × 4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows :
The clock to the register is shown, and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is
The clock to the register is shown, and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is
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