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GATE 2019: Digital Electronics Quiz 7 (App update required to attempt this test)
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Question 1
Consider the circuit given below. If all the flip-flops are initially cleared then the count 
after 8 clock pulses is
after 8 clock pulses is Question 2
The frequency at the output of the following cascaded circuit is …………. Hz.
Question 3
The given figure shows a ripple counter. If present state of the counter is Q2Q1Q0=101, then its next state (Q2Q1Q0) will be
Question 4
Assuming that all flip flop are in reset condition initially, the count sequence at Q2 in the circuit shown is
Question 5
A 4-bit serial-in-parallel-out shift register is used with a feedback as shown in figure. The shifting sequence is QA→QB→QC→QD
If the output is 0000 initially, the output repeats after
If the output is 0000 initially, the output repeats after
Question 6
How many different output state the following shift register is having, if the initial state is (Q3 Q2 Q1 Q0)= 0001
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Feb 15ESE & GATE EE
