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ISRO CS Quiz 4 : Computer Organization

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Question 1

The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called

Question 2

Consider the following data path of a simple non-pile lined CPU. The registers A,B, A₁, A₂, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bitregisters. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally

The CPU instruction “push r”, where = A or B, has the specification
M [SP] ←r
SP ←SP – 1
How many CPU clock cycles are needed to execute the “push r” instruction?

Question 3

The amount of ROM needed to implement a 4 bit multiplier is

Question 4

A processor needs software interrupt to

Question 5

A CPU generally handles an interrupt by executing an interrupt service routine

Question 6

Which of the following requires a device driver?

Question 7

Given the following relation instance.

                X       Y       Z 
                1       4       21      
                5       31      6     
                33      2       2

Which of the following functional dependencies are satisfied by the instance?

Question 8

Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?

Question 9

The most appropriate matching for the following pairs
X: Indirect addressing 1: Loops
Y: Immediate addressing 2: Pointers
Z: Auto decrement addressing 3: Constants

Question 10

The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is __________.

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GATE & PSU CS Computer Organization and Architecture

Apr 8GATE & PSU CS