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GATE EC : Digital Circuits Champion Quiz 2

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Question 1

In the following circuit, the switch S is closed at t = 0. The rate of change of current is given by

Question 2

A digital system is required to amplify a binary-encoded audio signal. The user should be able to control the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits required to encode, in straight binary is

Question 3

Which one of the following is the dual form of the Boolean identity given above?
Description: F:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE-ME-20-April\GATE-IES-EC-Digital=Electronics-Circuits_files\image054.png

Question 4

In the sum of products function f(X, Y, Z) = ∑(2, 3, 4, 5), the prime implicants are

Question 5

Choose the correct one from among the alternatives A,B,C,D after matching an item from Group 1 with the most appropriate item in Group 2.
Group 1
P. Shift register
Q. Counter
R. Decoder
Group 2
(1). Frequency division
(2). Addressing in memory chips
(3). Serial to parallel data conversion

Question 6

The two numbers represented in signed 2’s complement form are P = 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2’s complement form is

Question 7

In the following circuit, X is given by

Question 8

A 1–to–8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and Description: Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-2_files\image226.png to Description: Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-2_files\image227.png as the eight demultiplexed output, is to be designed using two 2–to–4 decoders (with enable input Description: Description: D:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE EC 10-Mar\GATE-ECE-2015-Paper-2_files\image228.png and address input A0 and A1) as shown in the figure Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R and S terminals should be

Question 9

The circuit diagram of a standard TTL NOT gate is shown in the figure. When Vi = 2.5 V, the modes of operation of the transistor will be:

Question 10

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible

Which of the following statements is true?
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Jul 20ESE & GATE EC