GATE CS : Operating Systems Champion Quiz 5 for GATE & PSU CS Exams

Question 1

The essential content(s) in each entry of a page table is/are

Question 2

A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual–to physical address translation, where the virtual address is used as follows
• bits 30–31 are used to index into the first level page table,
• bits 21–29 are used to index into the second level page table,
• bits 12–20 are used to index into the third level page table, and
• bits 0–11 are used as offset within the page.
The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively

Question 3

In which one of the following page replacement policies, Belady's anomaly may occur?

Question 4

A system uses FIFO policy for page replacement. It has 4 page frames with no pages loaded to begin with. The system first accesses 100 distinct pages in some order and then accesses the same 100 pages but now in the reverse order. How many page faults will occur?

Question 5

Where does the swap space reside?

Question 6

In the index allocation scheme of blocks to a file, the maximum possible size of the file depends on

Question 7

Consider a disk drive with the following specifications:
16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is

Question 8

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 msec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

Question 9

A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T₁), which occupies exactly one page. Each entry of T₁ stores the base address of a page of the second-level table (T₂). Each entry of T₂ stores the base address of a page of the third-level table (T₃). Each entry of T₃ stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
What is the size of a page in KB in this computer?

Question 10

Assume that there are 3 page frames which are initially empty. If the page reference string is 1, 2, 3, 4, 2, 1, 5, 3, 2, 4, 6, the number of page faults using the optimal replacement policy is__________.