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ISRO 2017 Computer Science : Computer Organization Quiz

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Question 1

In the absolute addressing mode

Question 2

In 8085 which of the following modifies the program counter?

Question 3

A hard disk with a transfer rate of 10 Mbytes/second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation?

Question 4

Consider a three word machine instruction
ADD A[R0], @ B
The first operand (destination) “A [R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@ B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is

Question 5

The micro instructions stored in the control memory of a process or have a width of 26 bits. Each micro instruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

Question 6

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches

Question 7

In a look-ahead carry generator, the carry generate function G_i and the carry propagate function P_i for inputs A_i and B_i are given by:

The expressions for the sum bit S_i and the carry bit C_i+1 of the look-ahead carry adder are given by:

where C₀ is the input carry.
Consider a two-level logic implementation of the look-ahead carry generator. Assume that all i and G i P are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with

and C₄ as its outputs are respectively:

Question 8

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1 : Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2 : Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3 : Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4 : Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?

Question 9

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers and it needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________

Question 10

Consider a machine with a 2–way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];

int i, j; /*Initialize array ARR to 0.0 */

for(i = 0; i < 1024; i++)

for(j = 0; j < 1024; j++)

ARR[i][j] = 0.0;
The size of double is 8 Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre–fetching is done. The only data memory references made by the program are those to array ARR.
The total size of the tags in the cache directory is

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GATE & PSU CS Computer Organization and Architecture

Jun 28GATE & PSU CS