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GATE CS 2018 - Digital Logic Quiz-10 ( Sequential Circuits-1)

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Question 1

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…) is__________.

Question 2

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is____________.

Question 3

Let k = 2ⁿ. A circuit is built by giving the output of an n-bit binary counter as input to an n to 2ⁿ bit decoder. This circuit is equivalent to a

Question 4

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

Question 5

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Qoutput of the JK flip-flop is connected to the inputof the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Whichone of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop.Both the flip-flops have non-zero propagation delays.

Question 6

The next state table of a 2-bit saturating up-counter is given below.

The counter is built as a synchronous sequential circuit using T flip-flops. The expression for

and

are

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GATE & PSU CS Digital Logic

Jul 23GATE & PSU CS