Access time of cache and main memeory are given as 41 ns and 51 ns respectively. If 71% of data (or instruction) is found in cache then what is the average read time (in ns)?
Question 2
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? I0 : MUL R2, R0, R1 ; R2R0 * R1 I1 : DIV R5, R3, R4 ; R5R3/R4 I2 : ADD R2,R5, R2 ; R2R5 + R2 I3 : SUB R5, R2, R6 ; R5R2 – R6
Question 3
Consider a computer system that stores floating-point numbers with 16-bit mantissa and an 8-bit exponent, each in two’s complement. The smallest and largest positive values which can be stored
Question 4
When two BCD numbers 0x14 and 0x08 are added what is the binary representation of the resultant number?
Question 5
If a square matrix. A satisfies ATA = I, then the matrix A is
Question 6
As compared to a BJT amplifier, an amplifier made using a JFET is likely to have
Question 7
Two random variables and are distributed according to (for and = 0 (otherwise) where a constant, is equal to
Question 8
The breakdown in a Bipolar Transistor is characterized by two parameters; breakdown voltage with emitter open Which one of the following is true?
Question 9
A signal source with 100 m wavelength is connected to the input terminals of a 150 m long transmission line terminated in its characteristic impedance. The phase difference between the voltages at two ends of the transmission line in steady-state condition is
Question 10
When signal frequency is 2000 KHz and IF is 455 KHz, the image frequency could be