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ISRO Exam CS 2017 Topic-Wise Quiz Computer Organization (Instruction Pipelining)
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Question 1
In X=(M+N×O)/(P×Q), how many one-address instructions are required to evaluate it?
Question 2
Consider a pipelined processor with the following four stages
lF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute WB: Write Back"
The IF, ID and WB stages take one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2
R1+R0
MUL R4, R3, R2 R4
R3*R2
SUB R6, R5, R4 R6
R5-R4
lF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute WB: Write Back"
The IF, ID and WB stages take one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2
R1+R0 MUL R4, R3, R2 R4
R3*R2 SUB R6, R5, R4 R6
R5-R4Question 3
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
1.Function locals and parameters
2.Register saves and restores
3.Instruction fetches
1.Function locals and parameters
2.Register saves and restores
3.Instruction fetches
Question 4
Register renaming is done in pipelined processors
Question 5
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is:
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