ESE EC 2018 Achiever Study Plan: Advanced Electronics Quiz 6

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Question 1

In a signal z(t), the odd part of a signal shows:

• Az(t) - z(-t)
• Bz(-t) + z(t)
• C2*(z(t)+z(-t))
• D1/2*[z(t)-z(-t)]

Question 2

If α is scaling factor for linear dimensions and β is scaling factor for supply voltage, then parasitic capacitance is scaled by:

• A1/β
• Bβ
• Cα + β
• D1/α

Question 3

Which among the following circuit has large noise margin which is suitable for And-OR-Invert function?

• ADCFL with buffer
• BDCFL
• CFET
• DSDCFL

Question 4

In a MOS equilibrium structure having 0.3eV as fermi potential of doped silicon substrate with silicon and metal electron affinity as 4.15eV and 4.1eV respectively, find the built in potential of the system?

• A-0.7eV
• B0.8eV
• C0.9eV
• D-0.9eV

Question 5

The number of cycles needed to execute for (i=1 to 2) {I₁;I₂;I₃;I₄;} in 4-stage pipeline processor with instructions I₁ I₂ I₃ I₄ having stages S₁, S₂, S₃, S₄ will be:

• A16
• B10
• C13
• D30

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