NIELIT Scientist –B Day-8 : Computer Organization Quiz-1

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Question 1

When performing booth’s Algorithm which types of the shifts are used

• ALogical Right Shift
• BArithmetic Left Shift
• CArithmetic Right Shift
• DLogical Left Shift

Question 2

Consider the following reservation table for a pipeline having three stages S₁, S₂ and S3.

The minimum average latency (MAL) is_________.

• A3
• B2
• C1
• D0

Question 3

Instructions execution in a processor is divided into 5 stages. Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2ns. Two pipelined implementations of the processor are contemplated.
(i) a naïve pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is _____.

• A0.43
• B1.50
• C2.31
• D3.23

Question 4

Consider a ‘k’ segment pipeline with clock cycle time as ‘Tp’. Let there be ‘n’ tasks to be completed in the pipelined processor. If this pipeline is treated to an ideal pipeline then the cycles per instruction(CPI) value for it is ______.

• A1
• B2
• C3
• D4

Question 5

The permissible latencies for a given 7 stage pipeline are 1, 3, 6. Greedy latency cycles are

• A1
• B3
• C8
• D(1, 3)

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