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Mission ISRO 2017 Day-12: Subjects Revision Test-2 (CO & DL )

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Question 1

For a binary half subtractor having two inputs A and B, the correct set of logical outputs DD(=A minus B) and X(=borrow) are

Question 2

The complement of the Boolean expression AB(C + AC) IS

Question 3

The minimum Boolean expression for the following circuit

Question 4

The excess-3 Code is also called

Question 5

The binary equivalent of the decimal number 42.75 is

Question 6

The output 0 and 1 level for TTL Logic family is approximately

Question 7

Logic family popular for low power dissipation

Question 8

Consider the following information about Microprocessor and Microcontroller, And Choose which statement is not valid
I. Microprocessors are used for big applications., Microcontrollers are used to execute a single task within an application.
II. Its power consumption is high because it has to control the entire system, It is built with CMOS technology, which requires less power to operate
III. It consists of CPU, RAM, ROM, I/O ports.,It doesn’t consist of RAM, ROM, I/O ports. It uses its pins to interface to peripheral devices.

Question 9

Consider these different types of flags in 8085 microprocessor and select which information is not correct
I. Sign flag(s)– If sign bit is 1 then the sign flag is set to 1 and if the sign bit is zero then flag is reset to zero.
II. Zero flag(z)– If the result of any arithmetic or logical operation is zero i.e. all the bits are zero then flag is set to 1 else it is set to zero.
III. Auxiliary carry– (AC) this flag is set to 1 only when a carry is produced in the result.
IV. Parity flag (P) – when the result of any operation has odd number of ones then parity flag is set to 1 else if it has even number of ones then it is reset to 0.
V. Carry flag(C) – This flag is set to 1 only when any intermediate carry is produced. Else it is reset to 0.

Question 10

Consider a pipelined processor with the following four stages
lF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute WB: Write Back"
The IF, ID and WB stages take one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2Description: E:\Gate\isro-cs\ISRO-CS-2009_files\image011.pngR1+R0
MUL R4, R3, R2 R4Description: E:\Gate\isro-cs\ISRO-CS-2009_files\image011.pngR3*R2
SUB R6, R5, R4 R6Description: E:\Gate\isro-cs\ISRO-CS-2009_files\image011.pngR5-R4

Question 11

Which is the example of CISC (.Complex Instruction Set Computer) processors

Question 12

How many number of times the instruction sequence below will loop before coming out of the loop?

      MOV AL, 00H

A1: INC AL
      JNZ A1

Question 13

Dirty bit for a page in a page table

Question 14

Disk requests are received by a disk drive for cylinder 5, 25, 18, 3, 39, 8 and 35 in that order. A seek takes 5 msec per cylinder moved. How much seek time is needed to serve these requests for a Shortest Seek First (SSF) algorithm? Assume that the arm is at cylinder 20 when the last of these requests is made 

Question 15

Complex Instruction Set Microprocessors (CISM) is _______________________________________
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Jun 18GATE & PSU CS