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GATE 2018 Exam: Digital Logic and CO
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Question 1
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is _________.
Question 2
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is
Question 3
Consider the following statements.
I. It increases the maximum I/O transfer rate
II. It reduces the interface by the DMA controller in the CPU’s memory access
III. It is beneficially employed for I/O devices with shorter bursts of data transfer
Which of the above statements are advantages of cycle stealing in DMA?
I. It increases the maximum I/O transfer rate
II. It reduces the interface by the DMA controller in the CPU’s memory access
III. It is beneficially employed for I/O devices with shorter bursts of data transfer
Which of the above statements are advantages of cycle stealing in DMA?
Question 4
The clock period of the pipelined processor is
Question 5
In case of direct mapping of cache, the mapping is expressed as _______
Question 6
Consider the following assembly code
Find number of true data dependencies in the above code
Find number of true data dependencies in the above code
Question 7
The logic circuit given below converts a binary code Y1Y2Y3 into
Question 8
Minimum number of 2-input NAND gates required to implement the function,
F= is
F= is
Question 9
By adding and these four numbers with different bases, what will be the result in Base 9?
Question 10
An X-Y flip flop, whose characteristic Table is given below is to be implemented using a J-K flip flop
This can be done by making?
This can be done by making?
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