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GATE-2018 live Quiz Session Questions: 24/01/2017
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Question 1
A Hypothetical control unit supports 5 groups of mutually exclusive signals
Find size of control memory (in bytes) using vertical programming if control unit support 256 control word memory.
Find size of control memory (in bytes) using vertical programming if control unit support 256 control word memory.
Question 2
For slow and inefficient I/O peripherals, the interrupt mechanism to be designed must be fast enough. The best possible choice for interrupt handling would be
Question 3
The following insructions in a pipeline are to be executed. Identify the hazards.
R1 <- R1+R2
R2 <- R3*R4
R3 <- R4-R1
R2 <- R3+R4
Question 4
Consider the C struct defined below:
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using
Question 5
How many times does the processor need to access the memory when it executes an indirect address of instruction?
Question 6
A + A’B + A’B’C + A’B’C’D + ......=
Question 7
The Boolean function Y= AB + CD is to realized using only 2-input NAND gates. The minimum number of gates required is .
Question 8
How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?
Question 9
110111, 10111 and 1110111 corresponds to the 2’s complement representation of the following set of numbers
Question 10
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Qoutput of the JK flip-flop is connected to the inputof the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Whichone of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop.Both the flip-flops have non-zero propagation delays.
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GATE & PSU CSGeneralJul 23GATE & PSU CS
