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ISRO EC 2018:Analog Circuits Booster Quiz 5
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Question 1
In an NMOS circuit, Vt = 4 V and VGS ranges from 7.5 to 10 V. The channel to be continuous, finds the largest value of VDS?
Question 2
In the given circuit, the silicon transistor has β = 75 and a collector voltage VC = 9V. Then the ratio of RB and RC is ________.
Question 3
The input signal Vin shown in the figure is a 1 KHz square wave voltage that alternates between +7V and -7V with a 50% duty cycle. Both transistors have the same current gain, which is large. The circuit delivers power to the load resistor RL. What is the efficiently of this circuit for the given input? Choose the closest answer.
Question 4
The feedback amplifier shown in fig. makes use of an op amp with internal gain (open loop gain) A = 105. How much is the output voltage for input signal vs = 2mV in the circuit shown.
Question 5
For the given n-channel MOSFET, determine the % decrease in the drain current at VGS = 1 V, if the n-channel between the two n-doped regions is removed.
Given that: IDSS = 8 mA, VP = -6 V, VT = 4 V.
Given that: IDSS = 8 mA, VP = -6 V, VT = 4 V.
Question 6
The hybrid equivalent circuit for a common-emitter configuration is given below.
Determine the parameters
for its equivalent 
model.
Determine the parameters
for its equivalent model. Question 7
The inverting op-amp shown in figure has an open loop gain of ‘15’. Find the closed loop gain VO/VS.
Question 8
A differential amplifier has an open circuit voltage gain of 100. This amplifier has a common input signal of 3.2V to both terminals and out put signal is 26mV.Determine the CMRR in dB
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Dec 9ESE & GATE EC
