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ISRO EC 2018:Analog Circuits Booster Quiz 3

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Question 1

For the n–channel enhancement MOSFET shown in Figure below, the threshold voltage V_th= 2 V. The rain current I_D of the MOSFET is 4 mA when the drain resistance R_D is 1 kΩ. If the value of R_D is increased to 4 Ω, drain current I_D will become

Question 2

In the circuit shown below,

voltage across the diode

and

Assume initially when switch S is open

then the incremental resistance in the circuit is ___________ Ω.

Question 3

For a common-base configuration of a BJT, the reverse voltage ratio is computed as:

Question 4

Which of the following JFET bias configuration will produce a load line parallel to the drain current axis in the transfer characteristics?

Question 5

For the circuit given below with an ideal operational amplifier, the maximum phase shift of the output V_out with reference to the input V_in is

Question 6

Which of the given points lie on the load line of the given network?

(1)

(2)

(3)

(4)

Question 7

For a p-channel JFET, determine the voltage applied between the gate and source terminal that will result in a drain current of 3 mA, Given,

Question 8

Find the value of R to design a RC phase shift oscillator to sustain oscillations of

and put C= 1nF?

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ESE & GATE EC Analog Circuits

Dec 9ESE & GATE EC