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ISRO 2018: Computer Organization Booster Quiz- 2
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Question 1
Consider the following statements related to 8085 Microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.
Choose which one is incorrect
Choose which one is incorrect
Question 2
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts l1, l2 and I3 require the following execution time after the interrupt is recognized :
(i) I1 requires 25 micro seconds
(ii) I2 requires 35 microseconds
(iii) I3 requires 20 microseconds
l1 has the highest priority and I3 has the lowest. What is the possible range of time for l3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
(i) I1 requires 25 micro seconds
(ii) I2 requires 35 microseconds
(iii) I3 requires 20 microseconds
l1 has the highest priority and I3 has the lowest. What is the possible range of time for l3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
Question 3
How many bytes and cycles are needed to store and execute this program by using RET INSTRUCTION
RET
PC15-8 = (SP)
SP = SP - 1
PC7-0 = (SP)
SP = SP - 1
RET
PC15-8 = (SP)
SP = SP - 1
PC7-0 = (SP)
SP = SP - 1
Question 4
Consider a pipelined processor with the following four stages
lF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute WB: Write Back"
The IF, ID and WB stages take one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2
R1+R0
MUL R4, R3, R2 R4
R3*R2
SUB R6, R5, R4 R6
R5-R4
lF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute WB: Write Back"
The IF, ID and WB stages take one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2
R1+R0 MUL R4, R3, R2 R4
R3*R2 SUB R6, R5, R4 R6
R5-R4Question 5
Consider the following Assembly language program':
MVIA 30 H
ACl 30 H
XRA A
POP H
After the execution of the above program, the contents of the accumulator will be
MVIA 30 H
ACl 30 H
XRA A
POP H
After the execution of the above program, the contents of the accumulator will be
Question 6
The most appropriate matching for the following pairs:
List - I
X: Indirect Addressing
Y: Immediate Addressing
Z: Auto Decrement Addressing
List – II
1. Loop
2. Pointers
3. Constants
List - I
X: Indirect Addressing
Y: Immediate Addressing
Z: Auto Decrement Addressing
List – II
1. Loop
2. Pointers
3. Constants
Question 7
Consider an uncompressed stereo audio signal of CD quality which is sampled at 44.1 kHz and quantized using 16 bits . What is required storage space if a compression ratio of 0.5 is achieved for 10 seconds of this audio?
Question 8
Consider a disk system with 100 cylinders. The requests to access the cylinders occur in the following sequence:
4, 34, 10, 7, 19, 73, 2, 15, 6, 20
Assuming that the head is currently at cylinder 50, what is the time taken to satisfy all requests if it takes 1ms to move from one cylinder to adjacent one and shortest seek time first policy is used?
4, 34, 10, 7, 19, 73, 2, 15, 6, 20
Assuming that the head is currently at cylinder 50, what is the time taken to satisfy all requests if it takes 1ms to move from one cylinder to adjacent one and shortest seek time first policy is used?
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Jun 27GATE & PSU CS
