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UGC-NET 2018: (Analog & Digital Circuits) SpeedTest Quiz 6
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Question 1
Which logic function has the output low only when both inputs are high?
Question 2
A counter in which all the flip-flops receive the clock pulse at the same time is known as
Question 3
Consider the following logic families:
1. MOS
2. CMOS
3. DTL
4. TTL
The correct sequence of power dissipation in increasing order is given by
1. MOS
2. CMOS
3. DTL
4. TTL
The correct sequence of power dissipation in increasing order is given by
Question 4
List-I
a. BJT
b. FET
c. SCR
d. Tunnel diode
List-II
i. Pinch off effect
ii. Controlled rectification
iii. Negative Resistance Characteristics
iv. Punch through effect
a. BJT
b. FET
c. SCR
d. Tunnel diode
List-II
i. Pinch off effect
ii. Controlled rectification
iii. Negative Resistance Characteristics
iv. Punch through effect
Question 5
CMRR (Common Mode Rejection Ratio) for a differential amplifier should be
Question 6
Consider the following devices:
1. BJT in CB mode
2. BJT in CE mode
3. JFET 4. MOSFET
The correct sequence of these devices in increasing order of their input impedance is
1. BJT in CB mode
2. BJT in CE mode
3. JFET 4. MOSFET
The correct sequence of these devices in increasing order of their input impedance is
Question 7
In LED, light is emitted, because ______.
Question 8
A UJT has
Question 9
The figure shows a half-wave rectifier. The diode D is ideal. The average steady-state current (in Amperes) through the diode is approximately ____________.
Question 10
A 1ms pulse can be stretched to 1 s pulse by using
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Dec 13ESE & GATE EC
