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GATE 2019 - Computer Organization Quiz-1 (Machine Instruction ) (App update required to attempt this test)

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Question 1

How long (in cycles) would the following sequence of instructions take to execute on an in-order processor with two execution units, each of which can execute any instruction? Load operations have a latency of two cycles, and all other operations have a latency of one cycle. Assume that the pipeline depth is 5 stages. \
LOAD r₁, ( r₂ )
ADD r₃ ,r₁ , r₄
SUB r₅, r₆ , r₇
MUL r_8,r₉ , r₁₀

Question 2

Consider the following code segment for a hypothetical CPU having 2 registers R1 and R2 :

Now consider 2 cases.

Case 1: Memory is byte addressable with word size = 64 bits. Program counter is loaded with decimal address of Let the value stored in PC while it was executing the HALT instruction be 'a'.

Case 2: Memory is word addressable with word size = 64 bits. Program counter is loaded with decimal address of 1000. Let the value stored in PC while it was executing the HALT instruction be 'b'.

Find the value of (a-b) ________

Question 3

How many times does the control unit refer to memory when it fetches and executes an indirect addressing mode instruction if the instruction is a computation type requiring an operand from memory.

Question 4

Assume there are 47 different opcodes, 32-registers in the machine. Every instruction has 2 registers as input and 1 register as output [opcode R1, R2, R3]. Find the number of bits to encode an instruction?

Question 5

Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction has one source operand in register and another operand in memory. Find number of bits to encode an instruction.

Question 6

Consider the following assembly code

Find number of true data dependencies in the above code

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