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GATE 2019 - Computer Organization Quiz-4 ( instruction Pipeline )

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Question 1

Consider a pipelined processor with stages IF, ID, EX and WB. IF, ID and WB stages takes one clock cycle each to complete the operation and EX stage depends on the instruction. ADD and SUB need 1 clock cycle. MUL and DIV need 3 clock cycles each. What is the number of cycles needed to execute the following sequence of instructions?
I0  : DIV R1,R2,R3;
I1  : MUL R4,R5,R6; 
I2  : SUB R2,R4,R1;   
I3  : ADD R6,R2,R5;
 
(Assume there is no hardware to reduce stalls)

Question 2

Consider a 4-stage pipeline with a respective delay of 10 ns, 40 ns, 20 ns and 30 ns. Interface register used between the stages have the delay of 5 ns. What is the performance gain of a pipeline?

Question 3

Consider an instruction pipeline which has the speed-up factor 7 which is operating at 80% efficiency. What could be the number of stages in the pipeline?

Question 4

Consider 4 segment instruction pipeline with the respective stage delay of 2ns, 6ns, 8ns, 3ns. What is the instruction execution role in the pipeline?

Question 5

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _________ percent.

Question 6

The time delay for four segment pipeline is t1 = 50ns, t2 = 45 ns, t3 = 95ns, t4 = 30ns. The interface register delay time is tr = 5ns. What would be the time to add 100 pairs of numbers in the pipeline.
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