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GATE 2019 - Computer Organization Quiz-6 ( Memory Organization )

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Question 1

What is transfer rate of serial transmission, if have 7 information bit and 1 start bit and 2 stop bit and 1 parity bit for each character and bit rate is 500bits /second ?  

Question 2

A Processor generates the following byte addresses 88,104,88,104,64,12,64,72. It has a very small Direct Map Cache with 4 Blocks of 4 bytes. Give the number of cache hits and cache miss respectively

Question 3

The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given clock rate is 100 MHz. Find the data rate (in MBps) of memory for transferring one block of memory.

Question 4

Given that 4 GB and 2 MB are the respective sizes of main memory and cache. Find the most appropriate tag bit length. Assume the block size is same in both cache and main memory and direct mapping is used with byte addressable memory.

Question 5

Consider a fully associative cache with 6 cache blocks (0 to 5) and the following sequence of memory block requests:
5, 4, 29, 18, 21, 7, 25, 18, 10, 35, 45, 22, 7, 16
If LRU replacement policy is used, which cache block is used for memory block 16? Assume initially 6 blocks are placed in a cache according to lexicographic order of cache index.

Question 6

A 2 way set associative write back cache with perfect LRU replacement requires 15 * 29 bits of storage to implement its tag (including bits for valid, dirty and LRU). If 5 tag bits for each tag and cache block size is 8 bytes, what is the size of the data stored on cache (in KB)?
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