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GATE CS 2019 - Digital Logic Quiz-7 ( Sequential Circuits-1)

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Question 1

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is ________.

Question 2

The output of both the flip-flops Q₁ and Q₂ in the figure shown below are initialized to 0. The sequence generated at Q₁ upon application of clock signal is

Question 3

In a 8 bit SISO register, if 16-bit data 1011 0101 0010 1010 is applied at the input. The minimum number of clock pulses required to transfer 16 bit data at the output is

Question 4

The shift register shown in figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left nost position (msb). After how many clock pulse will the content of the shift register became 1010 again?

Question 5

Consider the following synchronous counter made up of JK, D and T Flip-Flops.

The modulus value of the counter is ____________

Question 6

Arrange decade counter to obtain voltage of 1Khz from line frequency of 50 Hz

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GATE & PSU CS Digital Logic

Jun 10GATE & PSU CS