GATE CS 2019 : Computer Organization Quiz -1 (App update required to attempt this test)

Consider the following program segment used to execute in a RISC pipeline. All the instructions are spending one cycle in each and every stage but LOAD instruction takes 3 cycle on MA stage. How many cycles are required to complete the program execution____.

I1: LOAD r0, 3(r1)

I2: ADD r2, r1, r0

I3: LOAD r3, 2(r1)

I4: SUB r4, r3, r1

Consider a hypothetical pipelined processor with 4ns clock which uses delayed branch concept to optimize the control dependency pattern. If, not possible to optimize the problem, than the compiler substitute the 5 NOP instruction after the JMP instruction. If 30% of the instruction are branch instructions and among those, only 70% can be optimized, What is the average instruction execution time________ in nsec.

In a certain system the main memory access time is 100 ns. The cache is 10 times faster than the main memory and uses the write though protocol. If the hit ratio for read request is 0.92 and 85% of the memory requests generated by the CPU are for read, the remaining being for write; then the average time consideration for both read and write requests is ?

Assume it takes 30ns to search the associative registers and 100ns to access main memory. The percentage of slowdown in memory-access time is Y if the hit ratio is 75% then what is Y?

Consider a system with cache access time of 20ns and main memory access time of 140ns. If ‘x’% operations are read operations and the hit ratio for read operations is 90% then the effective memory access time is 74.6ns if write-through update technique is used. What is ‘x’ (approx..)?