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GATE CS 2019 : Computer Organization Quiz -2 (App update required to attempt this test)
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Question 1
If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio 90%).
Question 2
Pipelining is an implementation technique where multiple instructions are overlapped in execution. What among the given is the function of the pipeline
Question 3
A computer system implementsa 40-bit virtual address, page size of 8 kilobytes, and a 128-entry translation look-aside buffer (TLB) organized into 32 sets each having four ways. Assume that the TLB tag does not store any process id. The minimum length of the TLB tag in bits is ________.
Question 4
Consider the sequence of machine instructions given below:
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4
In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is__________.
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4
In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is__________.
Question 5
The following are four statements about Reduced Instruction Set Computer (RISC) architectures.
a) The typical RISC machine instruction set is small, and is usually a subset of a CISC instruction set.
b) No arithmetic or logical instruction can refer to the memory directly.
c) A comparatively large number of user registers are available.
d) Instructions can be easily decoded through hard-wired control units.
Which of the above statements is true?
a) The typical RISC machine instruction set is small, and is usually a subset of a CISC instruction set.
b) No arithmetic or logical instruction can refer to the memory directly.
c) A comparatively large number of user registers are available.
d) Instructions can be easily decoded through hard-wired control units.
Which of the above statements is true?
Question 6
Suppose there is a fully-associative write back cache that has number of cache entries that starts empty. The location is denoted in square brackets. Below is a sequence of operations
S1: Write M [100];
S2: Write M [100];
S3: Write M [200];
S4: Write M [200];
S5: Write M [100];
Then find out the number of misses when using no write allocate versus write allocate?
S1: Write M [100];
S2: Write M [100];
S3: Write M [200];
S4: Write M [200];
S5: Write M [100];
Then find out the number of misses when using no write allocate versus write allocate?
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