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GATE CS 2019 : Computer Organization Quiz -3
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Question 1
In a pipelined RISC computer, where arithmetic instructions and Load/store instructions are carried out, which of the following method will not definitely help in faster execution when only load/store instruction are performed?
Question 2
Regarding the different modes of data transfer, the throughput of CPU are measured: T1 for burst mode, T2 for cycle stealing mode, T3 for transparent DMA. Which of the following is best option?
Question 3
Consider 4-segement instruction pipeline where different instruction are spending different amount of time at different stages shown below:
What is the speedup?
What is the speedup?
Question 4
The program counter (PC) uses which of the following addressing mode?
Question 5
What is the average memory access time for a machine with a cache hit rate of 80% where the cache access time is 5ns and the memory access time is 50ns if simultaneous memory organization is used?
Question 6
Suppose a CPU contains 500 memory references. There are 50 misses in 
cache and 25 misses in the 
cache. Assume miss penalty from the 
cache to memory is 200 clock cycles and the hit time of 
cache is 20 clock cycles. The hit time of 
cache is 5 clock cycles. What is the average memory access time? (Assume simultaneous memory access is allowed)
cache and 25 misses in the cache. Assume miss penalty from the cache to memory is 200 clock cycles and the hit time of cache is 20 clock cycles. The hit time of cache is 5 clock cycles. What is the average memory access time? (Assume simultaneous memory access is allowed) - 379 attempts
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