GATE EE 2019: ThunderBolt Quiz 1

A transformer has a maximum efficiency of 98% at 15 kVA unity p.f. The daily load cycle of the transformer is as follows:

2kW load at 0.5 p.f. lagging for 12 hours

12 kW load at 0.8 p.f. lagging for 6 hours

18 kW load at 0.9 p.f. lagging for 6 hours

Calculate the all-day % efficiency of the transformer.

The figures in the network refer to capacitance in µF. If the combined capacitance is 5 µF, then find the value of C.

Find the voltage across the 100Ω resistor in the circuit shown below. Also, if the voltage across this resistor is to be reduced to 24 V, find the value of R which should be connected in parallel with it.

For the unbalanced delta connected load as shown, find the phase currents, line currents and the total power consumed by the load when the phase sequence is abc.

Three impedances are connected in delta to a 200V, 3 phase, three wire symmetrical system RYB, as shown. Calculate the reading on each wattmeter respectively. Assume phase sequence is RYB.

An N-channel FET with V_P = –2V and I_DSS = 1.75 mA is used in the amplifier as shown. Using a drain-source supply V_DD = 24V, it is desired to bias the circuit at I_D = 1 mA. Find V_GS, g_m and R_s.

A 4-pole DC generator supplies a current of 143 A. It has 492 armature conductors

(i) wave-wound (ii) lap-connected.

When delivering the full load, the brushes are given an actual lead of 10°. Calculate the demagnetizing amp-turns pole. This field winding is shunt connected and takes 10A. Find the number of extra shunt field turns necessary to neutralize this demagnetization.

If the input to the following ideal comparator is a sinusoidal signal of 8v (peak to peak) without any DC compute, the output of the comparator has a duty cycle of _______

Two Turbogenerator rated to 125 MW and 250 MW has governor drop characteristics of 10% from no load to full load each. They are connected in parallel to share a load of 300 MW. Determine the load shared by each machine assuming free governor action.

Assume the three T flip flops (T₂,T₁,T₀) whose have the output Q₂,Q₁ and Q₀ respectively. Realize the value of T₁ in terms of Q₂, Q₁, and Q₀ when these counters work as the synchronous counter with a counting sequence of states 0,1,2,4,5,6,0……..and so on.