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Digital Circuits Practice Quiz 2

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Question 1

The number of NAND gates required to implement AB + C will be

Question 2

Number of NAND gates required to implement NOT gate is

Question 3

Number of NOR gates required to implement OR gate.

Question 4

Number of NAND gates required to implement half adder carry function:

Question 5

The number of NOR gates required to implement XOR gate is:

Question 6

The output of logic shown below is:

Question 7

The expression for borrow in half subtractor is

Question 8

The number of NAND gates required for full adder is

Question 9

The output Y of the combinational logic shown below is

Question 10

The number of NOR gates used in the combinational logic shown below is-

Y = (A + B) (C + D)

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Aug 21ESE & GATE EC