GATE 2020 : Computer Organization & Architecture Quiz 5

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Question 1

The time delay for four segment pipeline is t1 = 50ns, t2 = 45 ns, t3 = 95ns, t4 = 30ns. The interface register delay time is tr = 5ns. What would be the time to add 100 pairs of numbers in the pipeline.

• A10.3 μs
• B22.9 μs
• C9.8 μs
• D9.9 μs

Question 2

Consider an instruction pipeline which has the speed-up factor 7 which is operating at 80% efficiency. What could be the number of stages in the pipeline?

• A7.33
• B4.5
• C10.6
• D8.75

Question 3

Consider the program segment consist of 100 instructions used to effect on 2 pipeline x & y. The execution time to execute of program on x pipeline is denoted as P1 & the execution time of the program on y pipeline is denoted as P2. Pipeline x consists of 5- stages with respective delays of 2ns, 8ns, 10ns, 6ns & 3ns. The pipeline y is having same number of stages with same amount of delay but stage -2 will be divided into 4-sub-stages of equal delays and stage-3 wil be divided into 3-substages of equal delays. Obtain the value of P1/P2?

• A1.29
• B1.79
• C1.59
• D2.69

Question 4

Consider two different implementations of the same instruction set architecture, P1 and P2. Processor P1 runs on a clock rate of 1.5 GHz and P2 runs on 2.0 GHz. There are four classes of instructions A, B, C and D; The CPI’s of each implementation are given in the following table.

Given a program with instructions divided into 4 classes according to the frequencies in the above table. Choose the correct statement from the following.

• AP1 is faster than P2
• BP2 is faster than P1
• CP1 is same as P2
• DNone of these

Question 5

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is_____________.

• A3.2
• B3.0
• C2
• D2.5

Question 6

Consider the following statements.
I. By passing can eliminate all stalls due to true data dependency.
II. In delayed branch condition the statement just above the branch instruction is executed after the branch condition.
Which of the above statement is/are correct.

• Aonly I
• Bonly II
• CBoth I and II.
• Dneither I nor II

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