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GATE CSE 2020: Revision Quiz 2 (App update required to attempt this test)
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Question 1
The clock period of the pipelined processor is
Question 2
Which among the following is the correct header length of IPv6 datagram?
Question 3
The program counter (PC) uses which of the following addressing mode?
Question 4
Which technique is used by 802.11 b HR-DSSS for data transfer?
Question 5
Which of the following assertions is FALSE about the Internet Protocol (IP)?
Question 6
An IP machine Q has a path to another IP machine H via three IP routers R1, R2, and R3.
Q—R1—R2—R3—H
H acts as an HTTP server, and Q connects to H via HTTP and downloads a file. Session layer encryption is used, with DES as the shared key encryption protocol. Consider the following four pieces of information:
[I1] The URL of the file downloaded by Q
[I2] The TCP port numbers at Q and H
[I3] The IP addresses of Q and H
[I4] The link layer addresses of Q and H
Which of I1, I2, I3, and I4 can an intruder learn through sniffing at R2 alone?
Q—R1—R2—R3—H
H acts as an HTTP server, and Q connects to H via HTTP and downloads a file. Session layer encryption is used, with DES as the shared key encryption protocol. Consider the following four pieces of information:
[I1] The URL of the file downloaded by Q
[I2] The TCP port numbers at Q and H
[I3] The IP addresses of Q and H
[I4] The link layer addresses of Q and H
Which of I1, I2, I3, and I4 can an intruder learn through sniffing at R2 alone?
Question 7
Ram and Sita uses the Diffie-Hellman Protocol for generating session key. Ram chooses y = 3 and Sita chooses x = 5. Identify session key value if G = 7 and N = 23
Question 8
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is _________.
Question 9
Which of the following is true about TLB?
I. Tag entry in TLB contains a virtual page number and each data entry of the TLB holds a physical page number.
II. TLB misses can be handled either in hardware or in software.
III. TLB miss or a page fault requires using the exception mechanism.
I. Tag entry in TLB contains a virtual page number and each data entry of the TLB holds a physical page number.
II. TLB misses can be handled either in hardware or in software.
III. TLB miss or a page fault requires using the exception mechanism.
Question 10
A system Jarvis requested for a specific site "gradeup.co", in return to this request it got the error as "LOOKUP FAILED". Now consider the following services:
1) SMTP
2) TCP
3) UDP
4) DNS
Which of the above service(s) are failed when we get the error as "LOOKUP FAILED"
1) SMTP
2) TCP
3) UDP
4) DNS
Which of the above service(s) are failed when we get the error as "LOOKUP FAILED"
Question 11
A group of some stations share a 56 kbps pure ALOHA channel. Each of these stations output a 1000 bits frame on an average of one every 100 seconds, even if the previous one not yet been sent. Efficiency of pure ALOHA is 18.4%. What would be the maximum number of stations?
Question 12
We have three stations P, Q, R connected in serial manner. P is connected to Q through a 3Gbps fibre optic link and length is 500Km. Q is connected to R through 60Mbps link and length is 15Km.All the links are full duplex in nature. A file is sent from station A to C. Packet size is 1KB.We use sliding window protocol such that SWS=RWS. Find the optimal SWS packets.
Question 13
Match the following:
Question 14
Consider 4-segement instruction pipeline where different instruction are spending different amount of time at different stages shown below:
How many cycles are required to complete the above instruction in case of a pipelined processor and also for non-pipelined processor?
How many cycles are required to complete the above instruction in case of a pipelined processor and also for non-pipelined processor?
Question 15
Cache Main memory = 64kb
Block size = 32B
Address size = 32 bit
Direct Mapping
What is the tag field size (Consider the cost of tag only)?
Block size = 32B
Address size = 32 bit
Direct Mapping
What is the tag field size (Consider the cost of tag only)?
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