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GATE CSE 2020 National Champion Quiz:Digital Logic (App update required to attempt this test)

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Question 1

With 3 Boolean variables, how many Boolean expressions can be formed.

Question 2

Find the value of the of following expression (in decimal).
(2)base 3 + (10)base 4 + (11)base 5 + (14)base 6 + (22)base 7

Question 3

What is the behavior of following one i/p Flipflop ‘X’ ?
seq1

Question 4

What is the minimum number of NAND gates required to implement the following boolean expression -
A' + B + C' + D

Question 5

Consider the following statements:
A multiplexer
1. selects one of the several inputs and transmit it to a single output.
2. routes the data from a single input to one of many output
3. converts parallel data into serial data.
4. is a combinational circuit
Which of the statements are correct?

Question 6

A digitial circuit which compares two numbers is shown in figure. To get output Y=0, choose one pair of correct input numbers.

Question 7

Which of the following is TRUE about formulae in Conjunctive Normal Form?

Question 8

The complete set of only those Logic Gates designated as Universal Gates is

Question 9

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, …, 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

Question 10

The simplified SOP (Sum of Product) form of the Boolean expression is

Question 11

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is____________.

Question 12

What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?
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Apr 17GATE & PSU CS