Time Left - 12:00 mins

ISRO CS 2019 : CO Booster Quiz 3

Attempt now to get your rank among 543 students!

Question 1

_______ is used to choose between incrementing the PC or Performing ALU operations.

Question 2

Given two binary strings with binary value 10011100 and 1010101 and some operation is performed on them and output according to it is -71. Code for ADD operation is 1, for SUB 2 , for AND 3 and XOR for 4. Give the integer code for correct operation.

Question 3

Consider a 16-bit register of floating format is used to store a floating-point number. Mantissa(M) is denoted as normalized signed magnitude fraction, exponent (E) is expresses as excess-64 form. Base of system is 2. How many bits are allocated for fractional Mantissa?

Question 4

A DMA module is transferring character to memory using cycle stealing, from a device transmitting at 12800 bps. The processor is fetching instructions at the rate of 4 million instructions per second. By how much (in %) will the processor slow down due to DMA activity?

Question 5

Is it true that IO module and main memory can exchange data directly without CPU involvement.

Question 6

Suppose that a datapath is built with the following latencies:
Instruction memory = 1200ps
Register file read = 130ps
ALU = 600ps
Data memory = 800 ps
Register file write = 400 ps
All other components = 0 ps.

Assuming an average CPI of 1.4 cycles, calculate the speedup of the pipelined implementation over the single-cycle implementation ?

Question 7

Consider the following sequence of instructions in the program:
Given stage1 (IF), stage2 (ID), stage3 (IE), stage4 (Memory access (MA)), stage5 (WB).
100: I1
101: I2 (JMP 200)
103: I3
.
.
.
200:BI1
What will be Output sequence of the above Instruction mention if there are any stalls?

Question 8

Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction has one source operand in register and another operand in memory. Find number of bits to encode an instruction.

Question 9

Consider the following assembly code

Find number of true data dependencies in the above code

Question 10

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

543 attempts
1 upvote
0 comments

Tags :

GATE & PSU CS Computer Organization and Architecture

Aug 1GATE & PSU CS