GATE EE 2021 : Digital Electronics Quiz 5 (App update required to attempt this test)

For the circuit given, if the clock frequency is ‘f’ Hz, then the frequency of the output Q is:

The frequency (in Hz) of the pulse at z in the network as shown in figure is-

A four bit serial in parallel out right register is shown in figure below. If the initial state (PQRS) of the shift register be (0110), then the minimum number of clocks/states required to again come to this value (0110) is

An x-y flip-flop, whose characteristic table is given below is to be implemented using J-K flip flop.

10 MHz clock frequency is applied is applied to a cascaded counter of MOD - 2, MOD - 5, MOD - 4 counter. what is the lowest output frequency (KHz)?

Each state is designated as Q₁Q₀ let initial state to be 00 then state transition sequence is _________.