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GATE EE 2021:Digital Electronics Quiz 9 (App update required to attempt this test)
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Question 1
A dual-slope A/D converter has a resolution of 4 bits. If the clock rate is 3.2 kHz, the maximum number of samples that can be converted in one second is ___?
Question 2
A dual slope A/D converter has a resolution of 12 bits. If the clock rate is 100 kHz then what is the worst case conversion rate of the circuit?
Question 3
A ramp type ADC has the following parameters, n = 5, Vref = 9.5 V, clock frequency = 1 MHz Assume the threshold voltage for the comparator is 4 mV. ________ is the digital word for an input voltage of 4 V.
Question 4
A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1μsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should be less than
Question 5
A temperature in the range of – 40o C to 55o C is to be measured with a resolution of 0.1o C. The minimum number of ADC bits required to get a dynamic range of the temperature sensor is
Question 6
A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is 0≤VIN ≤ 3Volts. The expression for the LSB of the output Bo as a Boolean function ofX2, X1, and Xo is
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ESE & GATE EEGeneralAug 17ESE & GATE EE