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ESE 2021 Technical Quiz 43 || Combinational Circuits

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Question 1

What are the output bits S (Sum) and C (Carry) of a Half Adder having inputs A = 1 and B = 1 ?
S C

Question 2

In which of the following adder circuits, the carry look ripple delay is eliminated?

Question 3

Consider the following statement:
For 3 input variables a, b, c; a Boolean function y=ab+bc+ca represents.
1). a 3-input majority gate
2). a 3-input minority gate
3). carry output of a full adder
4). product circuit for a, b and c.
Which of the above statement are correct?

Question 4

Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X and Z = 1 selects input Y. What are the connections required to realize the 2- variable Boolean function Description: F:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE-ME-20-April\GATE-IES-EC-Digital=Electronics-Circuits_files\image327.png, without using any additional hardware?

Question 5

The following switching functions are to be implemented using a decoder.
Description: F:\GradeStack Courses\GATE Tests (Sent by Ravi)\GATE-ME-20-April\GATE-IES-EC-Digital=Electronics-Circuits_files\image362.png
The minimum configuration of the decoder should be
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May 10ESE & GATE EC