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ESE 2021 Technical Quiz 44 || Sequential Circuits
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Question 1
Consider the given circuit,
In this circuit, the race around
In this circuit, the race around
Question 2
A 3 bit module-8 ripple counter uses JK flip-flop. If the propagation delay of each FF is 40ns, the maximum clock frequency that can be used is equal to
Question 3
For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT
Which of the following waveforms correctly represents the output at Q1?
Which of the following waveforms correctly represents the output at Q1?
Question 4
consider the circuit below with initial state Q0 = 1, Q1 = Q2 = 0. The state of the circuit is given by the value of 4Q2 + 2Q1 + Q0
which one of the following is the correct state sequence of the circuit?
which one of the following is the correct state sequence of the circuit?
Question 5
The input A and clock applied to the D flip-flop are shown in figure below. The output Q is
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May 11ESE & GATE EC