ESE 2021 Technical Quiz 45 || Sequential Circuits

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Question 1

Consider the circuit given below.

The duty cycle of is

• A20%
• B40%
• C30%
• D25%

Question 2

Consider the circuit given below


Assuming the initial value of counter output (Q₁, Q_o) as zero, the counter output for 8 clock pulses in decimal form is

• A0, 3, 2 ,1, 0, 1, 2, 3
• B0, 1, 2, 3, 2, 1, 0, 1
• C0, 1, 2, 3, 3, 2, 1, 0
• D0, 3, 2, 1, 0, 0, 1, 2

Question 3

The present output Q_n of an edge triggered JK flip-flop is logic 0. If J=1, then Q_{n +1}

• Acannot be determined
• Bwill be logic 0
• Cwill be logic 1
• Dwill race around

Question 4

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input „In‟ and an output ‘Out’. The initial state of the FSM is S0.

If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.

• A4
• B8
• C12
• D10

Question 5

What will be the frequency of the output if the input frequency is 200kHz?

• A50kHz
• B250Hz
• C125kHz
• D125Hz

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