GATE EC 2022:Digital Circuits Quiz 3

Attempt now to get your rank among 340 students!

Question 1

A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry. A 4 bit parallel adder is designed using this type of full adder. The maximum rate of additions per second can be provided by 4 bit parallel adder is Ax10⁶ additions/sec. The value of A is _____ .

• A44.4
• B4.44
• C0.44
• D5.44

Question 2

Consider the multiplexer based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?

• A
• B
• C
• D

Question 3

A 4-bit shift register circuit configured for right-shift operation, , is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

• A10
• B11
• C12
• D8

Question 4

The building block shown in fig. is a active high output decoder.

The output X is

• AAB +BC + CA
• BA + B + C
• CABC
• DNone of the above

Question 5

consider the following circuits (assume all gates have a finite propagation delay)
1)
2)
3)
4)
Which of these circuits generate a periodic square wave output?

• A1 and 2
• B2, 3 and 1
• C2 and 3
• D2, 3 and 4

Question 6

Consider a 3-bit number A and 2 bit number B are given to a multiplier. The output of multiplier is realized using AND gate and one bit full adders. If minimum number of AND gates required are X and one bit full adders required are then ________.

• A10
• B1
• C5
• D9

• 340 attempts
• 1 upvote
• 4 comments