Design for Testability, Examples

INTRODUCTION

An integrated circuit of a single-crystal chip of silicon, containing both active and passive elements and their interconnections. This chapter, concerned with the basic study of the integrated circuits, covers the following topics:

Basic Monolithic Integrated Circuit
Fabrication process of monolithic circuit
Epitaxial growth
Oxidation process: wet oxidation, dry oxidation
Masking and etching
Diffusion of impurities
Ion implantation
Thin-film deposition: evaporation, sputtering, chemical vapour deposition
PN junction diode fabrication
Monolithic integrated transistor and discrete planar epitaxial transistor

ADVANTAGE & DISADVANTAGE OF INTEGRATED CIRCUITS

Advantages of an Integrated Circuit over Discrete Circuits:

An integrated circuit quite small in size practically around 20,000 electronic components can be incorporated in a single square inch of IC chip.
Many complex circuits are fabricated on a single chip and hence this simplifies the designing of a complex circuit. And also, it improves the performance of the system.
IC’s will give high reliability. A lesser number of connections.
These are available at low cost due to bulk production.
IC’s consume very tiny power or less power.
It can easily replaceable from the other circuit.

Disadvantages of an Integrated Circuits:

After fabrication of an IC, it is not possible to modify the parameters within which an integrated circuit will operate.
When a component in an IC gets damaged, the whole IC has to be replaced by new one.
For higher value of capacitance (>30pF) in an IC, we should have to connect a discrete component externally
It is not possible to produce high power ICs (more than 10W).

FABRICATION OF A MONOLITHIC CIRCUIT

The monolithic circuit shown in Figure 1 is formed by the steps illustrated in Figure 2. The steps involved in the process are:

(i) Epitaxial Growth:

An n-type epitaxial layer, typically 25 microns thick, is grown onto a p-type substrate which has a resistivity of typically 10 Ω-cm, corresponding to N_A = 1.4 × 10¹⁵atoms/cm². After polishing and cleaning, a thin layer (0.5 micron = 5000 ) of oxide, SiO₂, is formed over the entire wafer, as shown in Figure 2 (a).

(ii) Isolation Diffusion:

In Figure 2 (b), the wafer is shown with the oxide removed in four different places on the surface. This removal is accomplished by means of a photolithographic process is used again to create the pattern of opening shown in Figure 2 (c).

(iii) Base Diffusion:

During this process, a new layer of oxide is formed over the wafer, and the photolithographic process is used again to create the pattern of openings shown in Figure 2 (c).

(iv) Emitter Diffusion:

A layer of oxide is gain formed over the entire surface, and the masking and etching process are used again to open windows in the p-type regions, as shown in Figure 2 (d).

(v) Alluminium Metallization:

In order to interconnect the various components of the integrated circuit, a fourth set of windows is opened into a newly formed SiO₂ layer, as shown in Figure 2 (e), at the points where contact is to be made. The interconnections are made first, using vacuum deposition of a thin even coating of aluminium over the entire wafer.

In the following sections, we will discuss these fabrication steps in some more detail.

EPITAXIAL GROWTH

The epitaxial process produces a thin film of single-crystal silicon from the gas phase upon an existing crystal wafer of the same material. The epitaxial layer may be either p-type or n-type, commonly formed from the vapour-phase decomposition of silicon tetrachloride (SiCl₄) or a silane compound (SiH₄, SiH₂Cl₂, SiHCl₃) in a reactor very similar to those employed in CVD. Additional Si literally grows following the lattice pattern of the pre-existing crystal. The basic chemical reaction used to describe the epitaxial growth of pure silicon is the hydrogen reduction of silicon tetrachloride.

ION IMPLANTAION

Ion implantation affords an alternative means of introducing dopants and other atoms into the near surface region of a semiconductor. In ion implantation an impurity is introduced into the semiconductor by creating ions of impurity, accelerating the ions to high energies ranging from 5 keV to 1 MeV, and then literally shooting the ions into the semiconductor.

Figure 6 shows the simplifies schematic of an ion implantation system.

The steps involved in the ion implantation are

Ions of the desired impurity are produced in the ion source shown at the extreme left.
The ions are next accelerated into the mass analyzer where unwanted ions, also produced in the ion source, are removed.
The resulting ion beam is then accelerated to the pre-set operating potential focused and finally scanned over the surface of the wafer,
An electrical contact to the wafer allows the flow of electrons to neutralize the implanted ions.

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