Basic Electronics Engineering : Junction and field effect transistors (BJT, FET and MOSFETS)

The article contains fundamental notes on "Junction and field effect transistors (BJT, FET and MOSFETS)"  topic of "Basic Electronics Engineering in  Electrical Engineering" subject. Also useful for the preparation of various upcoming exams like GATE Electrical Engineering(EE)/ IES/ BARC/ ISRO/ SSC-JE /State Engineering Services exams and other important upcoming competitive exams.

1.Basics of Mosfet:

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a field effect transistor (FET with an insulated gate) where the voltage determines the conductivity of the device. It is used for switching or amplifying signals. The ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. MOSFETs are now even more common than BJTs in digital and analog circuits.

Figure 1: Basic MOSFET structure

There are three possible regions for the working of the MOSFET.

1. Triode Region
2. Cut-off Region
3. Saturation Region

2.Drain Current Equation:

Where μ_n = mobility of electron

C_ox = Capacitance of oxide layer

   V_DS = drain to source voltage

2.1    Triode region

V_DS < V_GS – V_t    , if V_DS (mV)

2.2    Current Saturation

V_DS ≥ V_GS – V_t

(V_DS)_Sat = V_GS – V_t

→ g_m should be more, so k_n should be more μ_n → faster, gain → higher.

→ A good MOSFET should have high value of k_n

3.Operating Condition for MOSFET:

3.1.Operating Condition for N channel Enhancement type MOSFET:

3.2.Operating Condition for P channel Enhancement type MOSFET:

3.3.Operating Condition for N channel depletion type MOSFET:

3.4.Operating Condition for P channel depletion type MOSFET:

1. MOS Transconductance:

As a voltage-controlled source, a MOS transistor can be characterized by its transconductance

Various dependencies of g_m

5.Different biasing methods of MOSFET:

There are four biasing methods for MOSFET: -

1. Drain to gate bias
2. Voltage divider bias
3. Fixed bias
4. Self bias

5.1.Drain to gate bias configuration: -

Drain to gate bias Configuration

                DC Equivalent

DC Analysis-                  

Gate current , I_G =0

So, we have voltage drop across resistance R_G = V_RG = 0

Therefore, we get a direct connection between drain and source i.e.

V_D = V_G

_Note:

_{Drain to gate bias always enables MOSFET in saturation region}

For output circuit, we have

V_DS = V_DD – I_DR_D

5.2. Voltage divider bias configuration:

Voltage Divider Configuration

DC Equivalent

DC – ANALYSIS:

Using voltage divider, gate voltage is obtained by:

Applying KVL is loop 1, we get

V_G – V_GS – I_DR_S = 0

V_GS = V_G – I_DR_S …. (1)

Assume that MOSFET is in saturation, so we have I_D = K_n (V_GS – V_TN)²

By solving the quadratic equation, determine the value of V_GS or I_D, then apply KVL in source to drain loop

V_DD – I_DR_D – V_DS – I_SR_S = 0

V_DS = V_DD – I_D (R_S + R_D)

If V_DS > V_GS – V_TN, then the transistor is indeed biased in saturation region, as we have assumed.

However, if V_DS < V_{DS (sat),} then transistor is biased in the non saturation region

Therefore from equation (1)

V_GS = V_G – I_DR_S

5.3.Fixed bias configuration:

Fixed bias Configuration

DC Equivalent

(In DC model, R_G is short and input impedance is very high i.e. (I_G ≃ 0))

 DRAWBACK OF FIXED BIAS:

It is a dual battery design which makes it expensive and more space occupied bias Configuration.

5.4.Self bias configuration:

Self Bias Configuration

DC Equivalent

DC ANALYSIS:

0 = V_GS + I_DR_S

V_GS = – I_DR_S

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