Analog Electronics : BJT Biasing & Stabilization

1. ANALYSIS OF OPERATING MODE OF BJT

           Method-1

          To determine the mode of operation of a BJT, the following steps are followed.

          Step 1 :- Let Assume that the transistor is biased on the forward active mode,

          In this case put

                     V_BE = V_BE(ON), I_B > 0 and I_C = βI_B

          Step 2 :- Evaluate the linear circuit with these assumption.

          Step 3 :- Find the each terminal voltagesi.e., V_B, V_C and V_E.

          Step 4 :- Now, the BJT can be considered as two diodes connected back to back as shown below in figure 1

           Step 5 :- Inspect whether the diodes are  forward biased or reverse biased

           Step 6 :- Conclude the operating mode of transistor for the condition according given in table 1.

                      Method-2

       The mode of operation of the Transistor is found by follwing the given steps.

           Step 1 :- Assume  the transistor is biased in the forward active mode. In this case put

                                         V_BE = V_BE(ON), I_B>0 and I_C = βI_B

           Step 2 :- Evaluate the linear circuit with these assumption.

           Step 3 :- Determine the operating region by following condition

                                         V_CE > V_{CE (sat)}          Active region

                                         V_CE < V_{CE (sat)}          saturation region

            Method-3

           To determine the mode of operation of a BJT, the following steps are followed.

           Step 1 :- Assume the transistor is biased in the forward active region. In this case put

                          V_BE = V_BE(ON), I_B > 0 and I_C = βI_B

           Step 2 :- Determine the collector current, (I_C)_active for the transistor operating in active region.

           Step 3 :- Determine the value of collector current (I_C)_sat  in saturation mode.

           Step 4 :- Find the mode of operation by following the given below conditions.

                              (I_C)_sat < (I_C)_active       Saturation

                               (I_C)_sat > (I_C)_active        Active

2. OPERATING POINT

• From transistor characteristics, it is clear that a transistor functions most linearly when it is constrained to operate in its active region.
• To establish an operating point in the region it is necessary to provide approximate direct potentials and current, using external source.
• Once an operating point (also known as Quiescent or Q-point) is established, time varying excursions of input signal (base current, for example) should cause an output signal (Collector voltage as collector current) of the same waveform.
• If the output signal is not faithful reproduction of the input signal, for example, it is clipped on one side, then the operating point is unsatisfactory and should be relocated on the collector characteristics.
• Figure 3(a) shows the common emitter circuit (the capacitors have negligible reactance at the lowest frequency of operation of this circuit). Figure 3(b) gives the output characteristics of the transistor used in figure 3(a).
• Note that even if there are freedom to choose R_C, R_L, R_b and V_CC, it is not possible to operate the transistor everywhere in active region because various transistor ratings limit the range of useful operation.

3. THE DC AND AC LOAD LINES

The capacitance considered in the circuit of figure 3(a) is large enough so that they act as open circuits under DC conditions but short circuits at the lowest frequency of operation of the circuit. Since the capacitor are open-circuited under DC conditions so the circuit can be redrawn as shown below in figure 3(c)

     .....(i)

• Equation (i) represents the dc or static load line of the circuit with a slope of  –1/R_C as drawn in figure 3(b).
• If R_L = ∞ and if the input signal (base current) is large and symmetrical, operating point Q₁ must be located at the center of the load line. In this way, the collector voltage and current may vary approximately symmetrical around the quiescent values V_C and I_C, respectively.
• If R_L ≠ ∞, however, an ac or dynamic load line must be considered.
• Since capacitors act as short circuits at input signal frequency, the effective load at the collector becomes R_C in parallel with R_L.
• Now, AC or dynamic load line is defined as a line that passes through the dc operating point Q₁ and has a slope equal to 1/R'_L corresponding to the collector load. =R_C||R_L, Under AC conditions. This AC load line is indicated in figure 3(b).

4. INSTABILITY IN COLLECTOR CURRENT

From the above discussion, it is found that to obtain faithful reproduction of the input signal it should necessary to maintain a stable Q-point.

The collection current can be calculated by the following equation.

I_c = β I_B + (1+β) I_co …………(ii)

From equation (ii), It can be concluded that I_c is unstable due to the following reasons:

(i) Variations in I_co

I_co is the reverse saturation current of the collection function. It increases with an increase in temperature because of the increase in the concentration of minority carriers.

• If temperature increase by 1°C then I_co increases by 7%.
• For each 10°c rise in temperature I_co

Hence it is observed that variation in temperature causes change in I_co and as result, I_c also varies.

(ii) Variation in V_BE

 When temp increased 1°C, V_BE decreased by 2.5 mV.                 

Hence, changes in temperature create change in V_BE due to which base current (I_B) changes. Hence from equ. (ii) it can be concluded that collection current I_c also varies.

(iii) Variation in β

β varies w.r.t transistor replacement or due to variation in temperature.

• When a transistor is replaced with another transistor, β value will vary because it is practically difficult to find two transistors having exactly same value of β.
• For a given transistor, β also increases with an increase in temperature.

Hence from the above discussion, it can be concluded that I_c is unstable due to variation in I_co, β and V_BE i.e

I_c = f (I_CO, V_BE, β)                …………(iii)

From the above equation, It is clear that I_c is a function of I_co, β and V_BE. 

By Applying  partial differentiation on equation (iii),

ΔI_c = s.ΔI_co + s’ΔV_BE + s”Δβ ………….(iv)

Where s, s’ and s” are stability factors.

• From equation (iv), it can be conducted that for greater stability in I_c, ΔI_c should be smaller, which is possible when stability factors are smaller.
• Instability in I_c has two undesired effects:

          (i)   The operating point which changes along the load line may result in distorted output and some worst situations the operating point may move into cut off or saturation region.

          (ii)  Thermal runaway may occur which leads to damage of a BJT.

• Hence, collector current I_c should be made stable with either stabilization or compensation methods.

Procedure to find stability factor

Step 1: Find expression for I_B by applying KVL in a proper loop in the given circuit.

5. BJT BIASING

Biasing is a technique to make the Q-point (Quiescent point or operating point) stable with respect to temperature variation.

Commonly used biasing circuits are:

(i) fixed bias circuit

(ii) collector to base bias circuit

(iii) self-bias circuit

5.1.   Fixed bias circuit

In figure 4(a), the base current is derived from supply voltage V_cc by resister R_B. This type of biasing is called fixed bias as V_cc and R_B are fixed quantities.

The operating point Q₁ is chosen on load line for a particular Base current I_B as shown in figure 4 (c)

By applying KVL in input loop,       

Hence from above equ, Q-point (V_CE, I_C) is calculated for fixed I_B.

Stability factor

Disadvantage

• If β = 100, the stability factor is 101 and the collector current is 101 times that I_CO, reverse saturation current. Hence the stability factor for a fixed biased circuit is very high. So, it will be the least stable biasing arrangement.

5.2. Collector to base bias circuit

An improvement in bias stability is obtained if tapping for bias is taken from the collector terminal instead of from the collector supply point as shown in figure 5.

Applying KVL in input loop,

–V_CC + (I_B + I_C) R_c + I_BR_B + V_BE = 0

Now applying kVL in the output loop

–V_cc + R_c(I_B + I_c) + V_CE =0

With the help of above equ, operating point is calculated for given biasing circuit.

Stability factor

Advantage

• The stability factor is smaller than (β + 1), hence an improvement in stability is obtained over a fixed bias circuit.

Disadvantage

• The stability factor depends upon R_C. If R_c becomes smaller or zero, then the stability factor becomes very large and I_C does not remain stable.
• Resistance R_B connected from collector to base causes negative feedback due to which voltage gain of the amplifier's circuit decreases.

5.3. Self-bias or Voltage-Divider bias

• If the collector resistance R_c is very small, for example, in a transformer coupled circuit, then there is no improvement in stabilization in collector to base bias circuit over the fixed bias circuit.
• A circuit which can be used even if there is zero DC resistance in series with the collector terminal is self-biasing configuration of figure 6(a).
• The current in resistance R_E in emitter lead causes voltage drop which is in the direction of reverse biasing the emitter function.
• Since this function must be forward biased, the base voltage is obtained from supply through R₁, R₂

(Note: If R_b = R₁||R₂ → 0, then base to ground voltage V_BN is independent of I_CO. Under these circumstances  For best stability R₁ and R₂ must be kept as small as possible.)

• The given circuit in figure 6(a) can be simplified by using Thevenin’s theorem. Thevenin’s equivalent can be found between base and ground as shown in figure 6(b).

Now applying kVL in input loop

–V + I_B R_b + V_BE + (I_B + I_C) R_E = 0    

      By using    

Stability factor

Important point

• S varies between 1 for small R_b/R_E and 1 + β for R_b/R_E → infinity
• A smaller value of R_b, better for stabilization.

(Note: even if R_b becomes zero, the value of S can’t be reduced below unity. Hence I_c always increases more than I_co.)

• As R_b to reduced which Q-point to held fixed, the current drawn R₁, R₂ network from supply V_cc
• Also, if R_c is increased while R_b is held constant then V_cc must be increased to operate at the same Q-point.
• In either case, a loss of power (decreased efficiency) to disadvantage accompanies the improvement in stability.
• To avoid the loss of Ac (signal) gain because of feedback caused by R_c, this resistance is often passed by a large capacitance (> 10 μF), so that its reactance at frequencies under consideration is very small.

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