GATE 2022 Rapid Revision Quiz 1

A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction, 2 clock cycles for MUL instruction and 4 clock cycles for DIV instructions respectively. The number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used

The number of ways to distribute 6 different gifts to 2 students from total 4 students are ________.

For the matrix A =  , if the eigen vector is given as , then the value of p is:

The number of labelled binary trees that are there on the vertices {1, 2, 3, 4} that have only vertex 1 as a leaf and every binary trees has 4 nodes are ________.

In B+ tree root node consists (10, 20, 30, 40) as values, with leaf page L1 (2, 6), L2 (10, 13, 16, 17), L3 (20, 21, 23, 28), L4 (30, 32, 36, 38) and L5 (40, 54, 69 87). Suppose that a page can contain at most four data values, and then what would be the impact when the value 25 is inserted?

The logic circuit shown below implements

Computer A has 30 MB to send on a network and transmits the data in burst at 6 Mbps. The maximum transmission rate across routers in the network is 4 Mbps. If computer A’s transmission is shaped using a leaky bucket. What is the capacity (in MB) that the queue in the bucket must hold so that no data is discarded?